Switching Low Noise Amplifier

ABSTRACT

Disclosed are embodiments of an integrated circuit device design adapted to selectively amplify one of multiple received input signals. The device design resides on a machine readable medium, which is used by a design house, customer, or manufacturer to aid in the design and manufacture of at least one embodiment of the integrated circuit device. The device design incorporates at least two first stage transistors and a single second stage transistor. The first stage transistors are adapted to receive input signals from the same or different input signal sources and are each electrically coupled to the second stage transistor. A control circuit design is adapted to individually turn on a selected first stage transistor in conjunction with the second stage transistor, thereby activating a corresponding one of the cascode amplifiers and allowing the input signal received by the selected first stage transistor to be separately amplified.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation in part of U.S. application Ser. No.11/556,275 filed Nov. 3, 2006 and assigned to the present Assignee.

BACKGROUND

1. Field of the Invention

The embodiments of the invention generally relate to low noiseamplifiers for receiver circuits, and, more particularly, to a low noiseamplifier capable of accommodating multiple input signals.

2. Description of the Related Art

Cellular phone manufactures often need to accommodate several differentcellular standards (i.e., several different frequency bands). Thedifferent cellular standards are typically within the 800 MHz to 900 MHzrange and/or within the 1800 MHz to 1900 MHz range. Broadband wirelessdevices similarly may operate at several different standards (e.g.,several different Worldwide Interoperability for Microwave Access(WiMax) standards). The different WiMax standards are typically withinthe 2 to 11 GHz range and currently the focus is on 2.5 GHz, 3.5 GHz and5.8 GHz.

Systems (e.g., cellular or broadband wireless communication devices,test applications, radiometers, etc.) that accommodate multiplefrequencies, antennas and/or calibrated noise sources generally willhave a receiver circuit with multiple front ends. Each front end of thereceiver circuit incorporates a switch that provides a connectionbetween a specific device antenna or noise source and a correspondinglow noise amplifier (LNA). Each low noise amplifier is tuned to adesired frequency for noise figure and gain in order to amplify weaksignals emanating from that antenna or noise source. The frequency canbe the same or different for each low noise amplifier. For example,cellular or broadband wireless communication device, having a singleantenna, can incorporate multiple LNAs to allow for operation atmultiple different frequencies. Alternatively, a radar application canbe connected to multiple antennas via multiple LNAs that operate at thesame or different frequencies. The different front end switches allowthe receiver circuit to switch between different LNA inputs.

However, a number of problems are associated with incorporating multiplefront ends (i.e., switches to corresponding LNAs) into a receivercircuit. First, the multiple switches have loss, thereby adding to theoverall noise figure of the receiver circuit. Second, the multipleswitches and corresponding LNAs require additional space as well asadditional power supplies and control circuitries to turn them on andoff. Finally, additional switches are required at the output of each LNAand these additional switches similarly require additional space andcontrol circuitry.

SUMMARY

In view of the foregoing, disclosed herein are embodiments of anintegrated circuit device design adapted to selectively amplify one ofmultiple received input signals. The device design resides on a machinereadable medium, which is used by a design house, customer, and/ormanufacturer to aid in the design and manufacture of at least oneembodiment of the integrated circuit device.

The two stage integrated circuit device incorporates multiple firststage transistors and a single second stage transistor. The first stagetransistors are adapted to receive input signals from the same ordifferent input signal sources and are each electrically coupled to asingle second stage transistor, thereby forming multiple cascodeamplifiers having a common second stage transistor within the samedevice. Each of these cascode amplifiers can be tuned to the same ordifferent frequencies for noise figure and gain. Furthermore, a controlcircuit is adapted to selectively and individually turn on a selectedone of the first stage transistors in conjunction with the second stagetransistor, thereby activating a corresponding one of the cascodeamplifiers and allowing the input signal received by the selected firststage transistor to be separately amplified.

More particularly, the embodiments of the integrated circuit devicedesign comprise a first stage and a second stage. The first stagecomprises at least two transistors (i.e., first transistors) and thesecond stage comprises a single transistor (i.e., a second transistor).The transistors are all of a type suitable to be used for gain (e.g.,bipolar transistors, field effect transistors (FETs), high electronmobility transistors (HEMTs), nanotube transistors, etc.). Additionally,each of the transistors comprises a control node (e.g., a base of abipolar transistor, a gate of a FET, a gate of a nanotube transistor,etc.) and two additional nodes (e.g., a collector and emitter of abipolar transistor, a source and drain of a FET, a source and drain of ananotube transistor, etc.).

All of the first transistors in the first stage are electrically coupledto the second transistor in the second stage. Specifically, a selectedadditional node from the second transistor is electrically coupled to aselected additional node from each of the first transistors. Forexample, if the device comprises all bipolar transistors, then theemitter of the second bipolar transistor in the second stage iselectrically coupled to the collector of each first bipolar transistorin the first stage. Similarly, if the device comprises all n-type fieldeffect transistors, then the source of the second field effecttransistor in the second stage is electrically coupled to the drain ofeach first field effect transistor in the first stage and vice versa ifthe device comprises all p-type field effect transistors. Buy couplingeach of the first transistors to the second transistor in this manner,multiple cascode amplifiers having a common second stage transistor areformed within the same device. Each of the cascode amplifiers (i.e.,each combination of a first and second transistor) can be tuned to thesame or different frequencies for noise figure and gain.

The first transistors in the first stage are adapted to receive inputsignals from the same or different input signal sources. Each firsttransistor is further adapted to amplify an input signal and to transmitthat input signal, once amplified, to the second transistor in thesecond stage. The second transistor is adapted to further amplify theinput signal.

A control circuit design is electrically coupled to the secondtransistor and to each of the first transistors. The control circuit isadapted to selectively and individually turn on the first control nodesfrom any one of the first transistors simultaneously with the secondcontrol node of the second transistor such that only one input signal isamplified by the device at a time. For example, for a device comprisingbipolar transistors, the control circuit can be adapted to selectivelyturn on the first base for any one of the first bipolar transistors inthe first stage simultaneously with the second base for the secondbipolar transistor in the second stage. Similarly, for a devicecomprising field effect transistors, the control circuit can be adaptedto selectively turn on the first gate for any one of the first fieldeffect transistor in the first stage simultaneously with the second gatefor the second field effect transistor in the second stage. By turningon the control node of a selected first transistor and the control nodeof the second transistor simultaneously, a low noise cascode amplifieris activated for separately amplifying the input signal that is receivedby that one selected first transistor.

Furthermore, by allowing any of the first transistors to be selectivelyand individually turned on in conjunction with the second transistor,the cascode amplifiers can alternatively be activated on demand. Toaccomplish this, the control circuit is electrically coupled to thecontrol nodes of each of the first transistors and to the control nodeof the second transistor. This control circuit is adapted to turn on thesecond control node of the second transistor and to selectively andindividually turn on the first control node of each first transistor inresponse to different predetermined voltages. The control circuit isfurther adapted to short to ground all other input signals not beingprocessed.

The embodiments of the integrated circuit device, described above,provide for impedance matching through a plurality of first impedancematching circuits at the front end of the device and a second impedancematching circuit at the back end of the device. Specifically, a separatefirst impedance matching circuit is electrically coupled between thecontrol node of each of the first transistors (e.g., between the base orgate of a first bipolar or field effect transistor, respectively) andits corresponding input signal source. Additionally, a single secondimpedance matching circuit is electrically coupled to the output of thesecond transistor (e.g., at the collector or drain of a second bipolaror field effect transistor, respectively).

Also disclosed herein are embodiments of a method of amplifying multipleinput signals received by the same device. The embodiments compriseproviding a two stage integrated circuit device, as described above, inwhich a first stage of the device comprises a plurality of firsttransistors and a second stage of the device comprises a secondtransistor electrically coupled to each of the first transistors,thereby forming multiple cascode amplifiers within the same device. Eachof the different cascode amplifiers can be tuned to the same ordifferent frequencies for noise figure and gain.

Input signals are generated by one or more input signal sources andtransmitted to (i.e., received by) the first transistors. Impedancematching between the input signal source(s) and the first transistorscan be accomplished by transmitting each input signal to each of thefirst transmitters via a separate corresponding impedance matchingcircuit.

Then, a first control node of any one of the first transistors isselectively and individually turned on (e.g., by a control circuit inresponse to a predetermined voltage), as is the second control node inthe second transistor. As the first control node is selectively andindividually turned on, the input signals that are transmitted to all ofthe other first transistors are shorted to ground. By turning on thecontrol node of a selected first transistor and the control node of thesecond transistor simultaneously and by shorting the other input signalsto ground, a low noise cascode amplifier is activated for separatelyamplifying the input signal that is received by that one selected firsttransistor.

The processes of selectively and individually turning on the firstcontrol node of a first transistor and simultaneously turning on thesecond control node of the second transistor can be repeated for each ofthe first transistors in order to allow different cascode amplifiers(i.e., different combinations of first and second transistors) to beactivated on demand. This can be accomplished, for example, by a controlcircuit that turns on the first control nodes in response to differentpredetermined voltages.

These and other aspects of the embodiments of the invention will bebetter appreciated and understood when considered in conjunction withthe following description and the accompanying drawings. It should beunderstood, however, that the following descriptions, while indicatingpreferred embodiments of the invention and numerous specific detailsthereof, are given by way of illustration and not of limitation. Manychanges and modifications may be made within the scope of theembodiments of the invention without departing from the spirit thereof,and the embodiments of the invention include all such modifications.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the invention will be better understood from thefollowing detailed description with reference to the drawings, in which:

FIG. 1 is a block diagram illustrating embodiments of the integratedcircuit device of the invention;

FIG. 2 is a schematic diagram illustrating an embodiment of theintegrated circuit device of the invention;

FIG. 3 is a schematic diagram of a control circuit; and

FIG. 4 is a flow diagram illustrating an embodiment of a method of theinvention.

FIG. 5 is a an example design flow process of instantiating a designstructure comprising the integrated circuit device of the presentinvention into an IC design to create a final design structure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The embodiments of the invention and the various features andadvantageous details thereof are explained more fully with reference tothe non-limiting embodiments that are illustrated in the accompanyingdrawings and detailed in the following description. It should be notedthat the features illustrated in the drawings are not necessarily drawnto scale. Descriptions of well-known components and processingtechniques are omitted so as to not unnecessarily obscure theembodiments of the invention. The examples used herein are intendedmerely to facilitate an understanding of ways in which the embodimentsof the invention may be practiced and to further enable those of skillin the art to practice the embodiments of the invention. Accordingly,the examples should not be construed as limiting the scope of theembodiments of the invention.

As mentioned above, systems (e.g., cellular or broadband wirelesscommunication devices, test applications, radiometers, etc.) thataccommodate multiple frequencies, antennas and/or calibrated noisesources generally will have a receiver circuit with multiple front ends.Each front end of the receiver circuit incorporates a switch thatprovides a connection between a specific device antenna or noise sourceand a corresponding low noise amplifier (LNA). Each low noise amplifieris tuned to a desired frequency for noise figure and gain in order toamplify weak signals emanating from that antenna or noise source. Thefrequency can be the same or different for each low noise amplifier. Forexample, cellular or broadband wireless communication device, having asingle antenna, can incorporate multiple LNAs to allow for operation atmultiple different frequencies. Alternatively, a radar application canbe connected to multiple antennas via multiple LNAs that operate at thesame or different frequencies. The different front end switches allowthe receiver circuit to switch between different LNA inputs.

However, a number of problems are associated with incorporating multiplefront ends (i.e., switches to corresponding LNAs) into a receivercircuit. First, the multiple switches have loss, thereby adding to theoverall noise figure of the receiver circuit. Second, the multipleswitches and corresponding LNAs require additional space as well asadditional power supplies and control circuitries to turn them on andoff. Finally, additional switches are required at the output of each LNAand these additional switches similarly require additional space andcontrol circuitry. Therefore, there is a need in the art for a low noiseamplifier that is adapted to switch between multiple inputs signals.

In view of the foregoing, disclosed herein are embodiments of a singleon-chip low noise amplifier that is adapted to efficiently switchbetween multiple inputs signals, operating at the same or differingradio frequencies (RF), such that the signal to noise ratio (SNR) ismaximized prior to each input signal being amplified. The “switchable”low noise amplifier is designed as a two stage amplifier (i.e., twostage gain block) in which the first stage is capable of switchingbetween two or more different inputs.

More specifically, referring to FIG. 1, disclosed herein are embodimentsof a two stage integrated circuit device 100 that incorporates at leasttwo first stage transistors 110 and a single second stage transistor120. The first stage transistors 110 are adapted to receive inputsignals 160 from the same input signal source 150 or different inputsignal sources 150 a-c and are each electrically coupled to the singlesecond stage transistor 120. By coupling each first transistor 110 tothe second transistor 120, multiple cascode amplifiers 180 having acommon second stage transistor 120 are formed within the same device100. Each of these cascode amplifiers 180 can be tuned to the same ordifferent frequencies for noise figure and gain. Furthermore, a controlcircuit 170 allows the first stage transistors 110 to be selectively andindividually turned on in conjunction with the second stage transistor120 so any one of the multiple cascode amplifiers 180 can be activatedon demand in order to separately amplify the input signal 160 receivedby a selected first stage transistor 110.

More particularly, the first stage 101 of the device 100 comprises atleast two transistors 110 (i.e., first transistors) and the second stage102 of the device 100 comprises a single transistor 120 (i.e., a secondtransistor). The transistors 110, 120 are all of a type suitable to beused for gain (e.g., bipolar transistors, field effect transistors(FETs), high electron mobility transistors (HEMTs), nanotubetransistors, etc.). Additionally, each of the first transistors 110comprises a first control node 111 and two first additional nodes112-113. Similarly, the second transistor comprises a second controlnode 121 and two second additional nodes 122-123. For example, if thefirst and second transistors comprise bipolar transistors, then thecontrol node of each transistor is a base region and the additionalnodes are the collector and emitter regions. Similarly, if the first andsecond transistors comprise field effect transistors, then the controlnode of each transistor is a gate and the additional nodes are thesource/drain regions.

All of the first transistors 110 in the first stage 101 are electricallycoupled to the second transistor 120 in the second stage 102. Bycoupling the first transistors 110 to the second transistor 120,multiple cascode amplifiers 180 each having a common second stagetransistor 120 are formed within the same device 100. Specifically, aselected additional node 122 from the second transistor 120 iselectrically coupled to a selected additional node 113 from each of thefirst transistors 110. For example, if the first and second stages101-102 of the device 100 comprise bipolar transistors, then the emitterof the second bipolar transistor in the second stage is electricallycoupled to the collector of each first bipolar transistor in the firststage. Similarly, if the first and second stages 101-102 of the device100 comprise n-type field effect transistors, then the source of thesecond field effect transistor in the second stage is electricallycoupled to the drain of each first field effect transistor in the firststage and vice versa if the first and second stages comprise p-typefield effect transistors.

Each of the first transistors 110 in the first stage 101 is adapted toreceive an input signal 160. The input signal 160 that is received bythe different first transistors 110 within the first stage 101 can betransmitted from the same input signal source 150 or multiple differentinput signal sources 150 a-c. For example, each first transistor 110 canbe electrically coupled to and receive the same input signal from thesame antenna or noise source. Alternatively, each first transistor 110can be electrically coupled to and receive different input signals fromdifferent antennas and/or other noise sources. Each first transistor 110is further adapted to amplify the received input signal 160 and to thentransmit that input signal 160 to the second transistor 120 in thesecond stage 102. The second transistor 120 is adapted to furtheramplify the input signal 160.

A control circuit 170 is electrically coupled to the second transistor120 and to each of the first transistors 110 (e.g., via a plurality ofadditional transistors). This control circuit 170 is adapted toselectively and individually turn on the first control nodes 111 fromany one of the first transistors 110 in the first stage 101simultaneously with the second control node 121 of the second transistor120 in the second stage 102 such that only one input signal 160 isamplified by the device 100 at a time. For example, for a device 100comprising bipolar transistors, the control circuit 170 can be adaptedto selectively turn on the first base for any one of the first bipolartransistors in the first stage simultaneously with the second base forthe second bipolar transistor in the second stage. Similarly, for adevice 100 comprising field effect transistors, the control circuit 170can be adapted to selectively turn on the first gate for any one of thefirst field effect transistor in the first stage simultaneously with thesecond gate for the second field effect transistor in the second stage.By turning on the control nodes 111 of a selected first transistor 110and a second transistor 120 simultaneously, a corresponding low noisecascode amplifier 180 is activated for separately amplifying the inputsignal 160 that is received by that one selected first transistor 110.

Furthermore, by allowing any one of the first transistors 110 to beselectively and individually turned on in conjunction with the secondtransistor 120, the various cascode amplifiers 180 can alternatively beactivated on demand. Thus, only one input signal 160 will flow throughany one cascode amplifier 180 (i.e., through a selected first transistorand then through a second transistor) within the device 100 at a time.To accomplish this, the control circuit 170 is electrically coupled tothe control nodes 111 of each of the first transistors 110 and to thecontrol node 121 of the second transistor 120 (e.g., via a series ofadditional transistors). This control circuit 170 is adapted to turn onthe second control node 121 of the second transistor 120 and toindividually turn on the first control nodes 111 of the firsttransistors 110 in response to different predetermined voltages. Forexample, in response to 0 volts the control circuit may turn on thecontrol node of one first transistor and in response to 2.5 volts thecontrol circuit may turn on the control node of a different firsttransistors (see detail discussion below regarding FIG. 2). The controlcircuit 170 is further adapted to short to ground 178 all other inputsignals 160 not being processed. Shorting to ground all other inputsignals increase the isolation between those input signals not beingprocessed and the output of the device 100.

As mentioned above, each of the different cascode amplifiers 180 havinga common second stage transistors 120 within the device 100 (i.e., eachcombination of a first and second transistor) can be tuned to the sameor different frequencies for noise figure and gain. For example, incellular or broadband wireless communication applications the inputsignal 160 to each of the first transistors 110 can be from the sameinput signal source 150 (e.g., from the same antenna). However, in suchapplications the specified frequencies, at which each individual firsttransistor in series with the second transistor is tuned, can bedifferent. Thus, cellular devices can accommodate multiple standardswhich consist of several frequency bands, for example, within the 800MHz to 900 MHz and the 1800 MHz to 1900 MHz ranges. Similarly, broadbandwireless devices may accommodate multiple Worldwide Interoperability forMicrowave Access (WiMax) standards, which consist of several frequencybands that are typically within the 2 to 11 GHz range (e.g., 2.5 GHz,3.5 GHz and/or 5.8 GHz). Alternatively, in other types of applications,such as radar or test applications, the input signal 160 to each of thefirst transistors 110 can be from different input signal sources 150 a-c(e.g., from different antennas or calibrated noise sources). In suchapplications, the specified frequencies, at which each individual firsttransistor 110 in series with the second transistor 120 is tuned, can beeither the same or different, depending upon system objectives.

The embodiments of the integrated circuit device 100, described above,provide for impedance matching through a plurality of first impedancematching circuits 130 at the front end of the device 100 and a secondimpedance matching circuit 140 at the back end of the device 100.Specifically, a separate first impedance matching circuit 130 iselectrically coupled between the control node 111 of each of the firsttransistors 110 (e.g., between the base or gate of a first bipolar orfield effect transistor, respectively) and its corresponding inputsignal source 150 or 150 a-c. Additionally, a single second impedancematching circuit 140 is electrically coupled to the output node 123 ofthe second transistor 120 (e.g., at the collector or drain of a secondbipolar or field effect transistor, respectively). The impedancematching circuits 130 and 140 can comprise conventional matchingnetworks, transformers, etc., that are formed using conventionalimpedance matching techniques.

FIG. 2 is a schematic diagram illustrating an exemplary device 200according to the present invention. For illustration purposes, thetransistors depicted in FIG. 2 are bipolar transistors and is optimizedfor 20 GHz. However, as mentioned above, it is anticipated that anytransistor that can be used for gain (e.g., bipolar transistors, fieldeffect transistors, high electron mobility transistors, etc.) may beincorporated into the device 200. Additionally, while only two firststage transistors 210 a-b are illustrated, as mentioned above, it isanticipated that embodiments of the invention may be practiced with morethan two first stage transistors.

The integrated circuit device 200, as illustrated, comprises the threeports: two input ports through which input signals 260 a-b are receivedfrom one or more input signal sources 250 a-b (i.e., from the same ordifferent antennas and/or noise sources) and an output port 290. Anon-chip complementary metal oxide semiconductor (CMOS) control circuit270 is electrically coupled to the base 211 of each first transistor 210a-b and to the base 221 of the second transistor 220 via a plurality ofadditional transistors 271-277.

A voltage 279 (e.g., a 2.5 VDC voltage) is supplied to the bipolartransistors. The expected current draw is 14 mA. The current flows fromthe top half of the device 200 down to either the left half or the righthalf, depending upon the voltage biasing the gates of the n-channelmetal oxide semiconductor (NMOS) field effect transistors 272 and 275,in order to selectively turn on the control node 211 of either firsttransistor 210 a or first transistor 210 b. The biasing of the gates oftransistors 272 and 275 is complementary and is provided by the controlcircuit 270, for example, as illustrated in FIG. 3.

Specifically, the biasing of the gates of transistors 272 and 275 candepend upon predetermined voltages supplied to the gates of transistors372 and 375 of FIG. 3. For example, if 0 volts is supplied to the gatesof the transistors 372 and 375 of FIG. 3, then “/Control” is high,turning on transistor 272. This allows current to flow from transistor271 through transistors 272 and 273, thus biasing RF transistor 210 a inthe first stage 201 and RF transistor 220 in the second stage 202. Bybiasing transistor 210 a and transistor 220 simultaneously a path isprovided for signal 260 a on input #1 250 a to be amplified bytransistor 210 a in a common emitter configuration and then bytransistor 220 in a common base configuration (i.e., a cascode amplifieris formed on demand). In addition, transistor 277 is turned on toincrease isolation between the “off” input #2 250 b and the output 290by shorting the input signal 260 b to ground 278. Contrarily, if 2.5volts is supplied to the gates of transistors 372, 375 of FIG. 3, then“/Control” is low shutting off transistor 272 and turning on transistor275 of FIG. 2. This allows current to flow from transistor 271 throughtransistors 275 and 276, thus biasing RF transistor 210 b in the firststage 201 and RF transistor 220 in the second stage 202. By biasingtransistor 210 b and transistor 220 simultaneously a path is providedfor signal 260 b on input #2 250 b to be amplified by transistor 210 bin a common emitter configuration and then by transistor 220 in a commonbase configuration (i.e., a different cascode amplifier is formed ondemand). In addition, transistor 274 is turned on to increase isolationbetween the “off” input #1 250 a and the output 290 by shorting theinput signal 260 a to ground 278. A high degree of tracking isaccomplished because both sides of the “switch” are fabricated on onechip.

Referring to FIG. 4, also disclosed herein are embodiments of a methodof amplifying multiple input signals. The embodiments comprise providinga two stage integrated circuit device 100, as described above andillustrated in FIG. 1, in which a first stage 101 of the device 100comprises a plurality of first transistors 110 and a second stage 102 ofthe device 100 comprises a second transistor 120 electrically coupled toeach of the first transistors 110, thereby forming multiple cascodeamplifiers 180 (402).

Input signals 160 are generated by one or more input signal sources(e.g., one or more antennas and/or calibrated noise sources) andtransmitted to (i.e., received by) the first transistors 110 (404). Forexample, in cellular or broadband wireless communication applicationsthe input signal 160 received by each of the first transistors 110 canbe transmitted from the same input signal source 150 (e.g., from thesame antenna) that is electrically coupled to each of the firsttransistors 110 (405). Alternatively, in other types of applications,such as radar or test applications, the input signal 160 received byeach of the first transistors 110 can be transmitted from differentinput signal sources 150 a-c (e.g., from different antennas orcalibrated noise sources) that are each electrically coupled to adifferent corresponding first transistor 110 (406).

Impedance matching between the input signal source(s) 150 and the firsttransistors 110 can be accomplished by transmitting each input signal160 to each of the first transmitters 110 via a separate correspondingimpedance matching circuit 130 (408).

Then, a cascode amplifier 180 that is tuned to a specified frequency fornoise figure and gain is activated to separately amplify the inputsignal that is received by a selected one of the first transistors 110(410). Specifically, a first control node 111 of a specific one of thefirst transistors 110 is selectively and individually turned on (e.g.,by a control circuit in response to a predetermined voltage), as is thesecond control node 121 in the second transistor 120 (e.g., the base ofa second bipolar transistor or the gate of a second field effecttransistor) (411-412). As the first control node 111 is selectively andindividually turned on, the input signals 160 that are transmitted toall of the other first transistors 110 are shorted to ground 178 (413).By turning on the control nodes 111, 121 of a specific one of the firsttransistors 110 and of the second transistor 120 simultaneously and byshorting the other input signals to ground at process 411-413, a lownoise cascode amplifier 180 is activated for separately amplifying theinput signal that is received by that one selected first transistor 110.

The processes 411-413 of selectively and individually turning on thefirst control node 111 of a first transistor 110 and simultaneouslyturning on the second control node 121 of the second transistor 120 canbe repeated for any other first transistor 110 in order to allowdifferent cascode amplifiers (i.e., different combinations of first andsecond transistors) to be activated and, thereby to separately amply theinput signals received by different first stage transistors (414). Thiscan be accomplished, for example, by a control circuit 170 that turns ondifferent first control nodes 111 in response to different predeterminedvoltages.

The cascode amplifiers 180 that are activated at processes 410 and 414can be tuned to the same or different frequencies for noise figure andgain. For example, in cellular or broadband wireless communicationapplications the input signal to each of the first transistors can befrom the same input signal source (e.g., from the same antenna).However, in such applications the specified frequencies, at which eachindividual first transistor in series with the second transistor istuned, can be different. Alternatively, in other types of applications,such as radar or test applications, the input signal to each of thefirst transistors can be from different input signal sources (e.g., fromdifferent antennas or calibrated noise sources). In such applications,the specified frequencies, at which each individual first transistor inseries with the second transistor is tuned, can be either the same ordifferent, depending upon system objectives.

Therefore, disclosed above are embodiments of a two stage integratedcircuit device adapted to selectively amplify one of multiple receivedinput signals and an associated method. Specifically, the integratedcircuit device incorporates at least two first stage transistors and asingle second stage transistor. The first stage transistors are adaptedto receive input signals from the same or different input signal sourcesand are each electrically coupled to the single second stage transistor,thereby forming multiple cascode amplifiers each having a common secondstage transistor. Each of these cascode amplifiers can be tuned to thesame or different frequencies for noise figure and gain. Furthermore, acontrol circuit is adapted to selectively and individually turn on aselected one of the first stage transistors in conjunction with thesecond stage transistor, thereby activating a corresponding one of thecascode amplifiers and allowing the input signal received by theselected first stage transistor to be separately amplified. Theseembodiments eliminate the loss of the switch or coupler as well as theneed for multiple low noise amplifiers. Additionally, the device lowersthe overall receiver noise figure by eliminating the loss of the switchin the front end. Those skilled in the art will recognize that theamount of reduction depends on the frequency of operation and can, forexample, be between 0.5 to 1 dB.

FIG. 5 shows a block diagram of an example design flow 500. Design flow500 may vary depending on the type of IC being designed. For example, adesign flow 500 for building an application specific IC (ASIC) willdiffer from a design flow 500 for designing a standard component. Designstructure 520 is an input to a design process 510 and may come from anIP provider, a core developer, or other design company. Design structure520 comprises integrated circuit device 200 in the form of schematics orHDL, a hardware-description language, (e.g., Verilog, VHDL, C, etc.).Design structure 520 may be on one or more of machine readable medium,for example, an electronic file on a hard drive or a CD ROM. Designstructure 520 may, for example, be a text file or a graphicalrepresentation of integrated circuit device 200. Design process 510synthesizes (or translates) integrated circuit device 200 into a netlist580, where netlist 580 is, for example, a list of I/O, library modules,wires, transistors, etc. and describes the connections to other elementsand circuits in an integrated circuit design and recorded on at leastone of machine readable medium.

Design process 510 includes using a variety of inputs; for example,inputs from library elements 530 which may house a set of commonly usedelements, circuits, and devices, including models, layouts, and symbolicrepresentations, for a given manufacturing technology (e.g. differenttechnology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 540,characterization data 550, verification data 560, design rules 570, andtest data files 585, which may include test patterns and other testinginformation. Design process 510 further includes, for example, standardcircuit design processes such as timing analysis, verification tools,design rule checkers, place and route tools, etc. One of ordinary skillin the art of integrated circuit design can appreciate the extent ofpossible electronic design automation tools and applications used indesign process 510 without deviating from the scope and spirit of theinvention.

Ultimately design process 510 translates integrated circuit device 200,along with the rest of the integrated circuit design (if applicable),into a final design structure 590 (e.g., information stored in a GDSstorage medium). Final design structure 590 may comprise informationsuch as, for example, test data files, design content files,manufacturing data, layout parameters, wires, levels of metal, vias,shapes, test data, data for routing through the manufacturing line, andany other data required by a semiconductor manufacturer to produceintegrated circuit device 200. Final design structure 590 may thenproceed to a stage 595 of design flow 500; where stage 595 is, forexample, where final design structure 590: proceeds to tape-out, isreleased to manufacturing, is sent to another design house or is sentback to the customer.

The foregoing description of the specific embodiments will so fullyreveal the general nature of the invention that others can, by applyingcurrent knowledge, readily modify and/or adapt for various applicationssuch specific embodiments without departing from the generic concept,and, therefore, such adaptations and modifications should and areintended to be comprehended within the meaning and range of equivalentsof the disclosed embodiments. It is to be understood that thephraseology or terminology employed herein is for the purpose ofdescription and not of limitation. Therefore, those skilled in the artwill recognize that the embodiments of the invention can be practicedwith modification within the spirit and scope of the appended claims.

1. A design structure instantiated in a machine readable medium fordesigning and manufacturing an integrated circuit device; the integratedcircuit device comprising: a plurality of first transistors, whereineach of said first transistors comprises a first control node; a secondtransistor comprising a second control node, wherein each of said firsttransistors is adapted to receive and amplify an input signal and totransmit said input signal to said second transistor, wherein saidsecond transistor is adapted to further amplify said input signal; and acontrol circuit electrically coupled to said second transistor and toeach of said first transistors, wherein said control circuit is adaptedto selectively and individually turn on said first control node of onlyone of said first transistors simultaneously with said second controlnode such that only one input signal is amplified at a time.
 2. Theintegrated circuit device of claim 1, further comprising a plurality offirst impedance matching circuits, wherein each one of said firstimpedance matching circuits is electrically coupled between an inputsignal source and one of said first transistors.
 3. The integratedcircuit device of claim 1, further comprising a second impedancematching circuit electrically coupled to said second transistor.
 4. Theintegrated circuit device of claim 1, wherein said control circuit isfurther adapted to turn on said second control node in conjunction withsaid first control node of each of said first transistors, individually,in response to different predetermined voltages.
 5. The integratedcircuit device of claim 1, wherein when selectively and individuallyturned on, said first transistors in series with said second transistorform cascode amplifiers and wherein said cascode amplifiers are tuned tospecified frequencies for noise figure and gain.
 6. The integratedcircuit device of claim 5, wherein said input signal received by each ofsaid first transistors is transmitted from a single input signal source,and wherein said specified frequencies are different.
 7. The integratedcircuit device of claim 5, wherein said input signal received by each ofsaid first transistors is transmitted from different input signalsources, and wherein said specified frequencies are the same.
 8. Theintegrated circuit device of claim 5, wherein said input signal receivedby each of said first transistors is transmitted from different inputsignal sources, and wherein said specified frequencies are different. 9.The integrated circuit device of claim 1, wherein said first transistorsand said second transistor each comprise a transistor of a type suitableto be used for gain.
 10. A design structure instantiated in a machinereadable medium for designing and manufacturing an integrated circuitdevice, the integrated circuit device comprising: a plurality of firstbipolar transistors, wherein each of said first bipolar transistorscomprises a first base; a second bipolar transistor comprising a secondbase, wherein each one of said first bipolar transistors is adapted toreceive and amplify an input signal and to transmit said input signal tosaid second bipolar transistor, wherein said second bipolar transistoris adapted to further amplify said input signal; and a control circuitelectrically coupled to said second bipolar transistor and each of saidfirst bipolar transistors, wherein said control circuit is adapted toselectively and individually turn on said first base of only one of saidfirst bipolar transistors simultaneously with said second base such thatonly one input signal is amplified at a time.
 11. The integrated circuitdevice of claim 10, further comprising a plurality of first impedancematching circuits, wherein each one of said first impedance matchingcircuits is electrically coupled between an input signal source and oneof said first bipolar transistors.
 12. The integrated circuit device ofclaim 10, further comprising a second impedance matching circuitelectrically coupled to said second bipolar transistor.
 13. Theintegrated circuit device of claim 10, wherein said control circuit isfurther adapted to turn on said second control node in conjunction withsaid first control node of each of said first transistors, individually,in response to different predetermined voltages.
 14. The integratedcircuit device of claim 10, wherein when selectively and individuallyturned on, said first bipolar transistors in series with said secondbipolar transistor form cascode amplifiers and wherein said cascodeamplifiers are tuned to specified frequencies for noise figure and gain.15. The integrated circuit device of claim 14, wherein said input signalreceived by each of said first bipolar transistors is transmitted from asingle input signal source, and wherein said specified frequencies aredifferent.
 16. The integrated circuit device of claim 14, wherein saidinput signal received by each of said first bipolar transistors istransmitted from different input signal sources, and wherein saidspecified frequencies are the same.
 17. The integrated circuit device ofclaim 14, wherein said input signal received by each of said firstbipolar transistors is transmitted from different input signal sources,and wherein said specified frequencies are different.
 18. A designstructure instantiated in a machine readable medium for designing andmanufacturing an integrated circuit device, the integrated circuitdevice comprising: a plurality of first field effect transistors,wherein each of said first field effect transistors comprises a firstgate; a second field effect transistor comprising a second gate, whereineach one of said first field effect transistors is adapted to receiveand amplify an input signal and to transmit said input signal to saidsecond field effect transistor, wherein said second field effecttransistor is adapted to further amplify said input signal; and acontrol circuit electrically coupled to said second field effecttransistor and each of said first field effect transistors, wherein saidcontrol circuit is adapted to selectively and individually turn on saidfirst gate of only one of said first field effect transistorssimultaneously with said second gate such that only one input signal isamplified at a time
 19. The integrated circuit device of claim 18,further comprising a plurality of first impedance matching circuits,wherein each one of said first impedance matching circuits iselectrically coupled between an input signal source and one of saidfirst field effect transistors.
 20. The integrated circuit device ofclaim 18, further comprising a second impedance matching circuitelectrically coupled to said second field effect transistor.